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FPGA
/ CPLD development
suite for Xilinx devices
Due to fast changes and improvements these hints should give an overview, intention is not to give users a step by step instruction list.
Links to FPGA software packages and documentation below can be found at: http://www.seng.de/dlk_database.html > Xilinx FPGA links
Links to FPGA demo projects can be found at: http://www.seng.de/eLAB_applications.html > eLABbase (FPGA)
Links to CPLD demo projects can be found at: http://www.seng.de/eLAB_applications.html > eMOD-d (CPLD)
Install:
Due to fast changes and improvements these hints should give an overview, intention is not to give users a step by step instruction list.
Links to FPGA software packages and documentation below can be found at: http://www.seng.de/dlk_database.html > Xilinx FPGA links
Links to FPGA demo projects can be found at: http://www.seng.de/eLAB_applications.html > eLABbase (FPGA)
Links to CPLD demo projects can be found at: http://www.seng.de/eLAB_applications.html > eMOD-d (CPLD)
Install:
- install dlk51 (eLABbase control program)
- download and install "WebPACK ISE" and "ModelSim XE" (free software which provides everything you need to complete a Xilinx CPLD or FPGA design)
Use (FPGA):
- (download FPGA demo project)
- load project into WebPACK ISE, or create new project
- compile (create *.bit configuaration file, default)
- run dlk51 >
FPGA > Config via PC ... (download *.bit configuration file to
eLABbase FPGA)
Use (external CPLD):
- (download CPLD demo project)
- load project into "WebPACK ISE", or create new project
- compile (create *.jed configuration file, default)
- run dlk51 > Command > Emulate > DLC5 / Parallel Cable III (load external DLC5 / Parallel Cable III emulation)
- connect CPLD board to
eLABbase (P5...P8) JTAG port
- run "iMPACT" programming software (part of "WebPACK ISE")
- erase CPLD via (iMPACT) (erase CPLD, override write protect)
- program CPLD via "iMPACT" (program *.jed file to CPLD)
Use (eLABbase/dlk51 internal CPLD, for update and test purposes only):
- Attention: programming not
valid code to internal CPLD may lead to not bootable board or
produce severe damage to the board
- run dlk51 >
FPGA > Config via PC ...
- select "intdlc5.bit" FPGA configuration file (load internal DLC5 / Parallel Cable III emulation)
- run "iMPACT" programming software (part of "WebPACK ISE")
- erase CPLD via (iMPACT) (erase CPLD, override write protect)
- program CPLD via "iMPACT" (program *.jed file to CPLD)
have fun !!!