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dlk -
boot-logic The boot information for a ´dlk´ system comes out of a standard Flash-memory. The memory contains FPGA configuration data and the program memory of the CPU. Control of the boot sequence is done by a state machine realized in a non volatile, flash-based, CPLD.
- several different FPGA configurations and several CPU programs can be saved in one single Flash-memory
- the selection of the FPGA configuration file in Flash-memory is done by external signals or jumpers
- the selection of the CPU program in Flash-memory is done by configurable logic within the FPGA
- fast boot procedure of FPGA's due to parallel data path
- use of inexpensive standard Flash-memory, dual-used for FPGA and CPU
- comfortable programming and update of boot-logic via ´dlk´ internal JTAG emulation
- use of inexpensive standard CPLD, not-used internal
resources are available for user application